1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and in more particularly relates to a method for fabricating a gate electrode of a semiconductor device having reduced polysilicon gate depletion.
2. Description of the Related Art
Semiconductor devices such as field effect transistors (FETs) are increasingly being used in low voltage applications. As semiconductor devices are fabricated to have a higher degree of integration, a faster operating speed, and lower power consumption, the magnitude or size of a complementary metal-on semiconductor field effect transistor (CMOSFET, hereafter referred to as “CMOS”) included in the device is rapidly reduced. As CMOS devices are scaled to smaller and smaller dimensions, manufacturers must refine transistor designs to maintain optimum device performance.
The conventional method of fabricating CMOS devices comprises polysilicon layers doped by impurity implantation to form polysilicon gate electrodes such as NMOS or PMOS gate electrodes. If the polysilicon gate electrode is over-implanted with dopants such as arsenics or boron, a complete conductor is not formed and polysilicon gate depletion increases. During operation of the MOS transistor, a depletion region may thus arise due to depletion of electric charge at an interface between the gate oxide layer and the substrate. The depletion region of the polysilicon gate has a magnitude of several angstroms (Å) and acts as a connected gate oxide layer capacitor. If the thickness of a gate oxide layer is small, the characteristics such as device current of the transistor are poor due to the polysilicon-gate-depletion region.
Structures and fabrication methods have therefore been explored to solve the above-discussed problems. U.S. Patent No. 2006/0030109 describes a method for producing highly doped polysilicon thin films as shown in FIG. 1. In the conventional process a bi-layer polysilicon gate electrode 226 for an n-type device comprising a lower highly doped n-type polysilicon film 222 and an upper n-type polysilicon gate electrode 240 is fabricated along with the formation of a n-type source/drain region 242. A highly doped bi-layer polysilicon gate electrode 228 for a p-type device comprising a lower highly doped p-type polysilicon film 220 and an upper p-type polysilicon film 244 is fabricated along with the formation of a p-type source/drain region 246. A high temperature or long duration annealing process is not required to drive the gate electrode/gate dielectric interface. A lower energy and heavy implantation process is difficult to control. The penetration of dopants through the gate oxide must be improved.
U.S. Pat. No. 6,930,362 B1 discloses a calcium doped polysilicon gate electrode for PMOS containing semiconductor devices. The physical/chemical attraction between calcium and boron inhibits movement of boron out of the polysilicon gate electrode material, thereby reducing boron penetration and polysilicon depletion problems and also improving device performance. An additional calcium implantation process and an appropriate calcium/boron ratio are thus required in the PMOS fabricating process.
Thus, a novel and reliable method of fabricating a gate electrode of a semiconductor device for reducing polysilicon gate depletion is desirable.